SH7730 Datasheet, PDF (465/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
16
15, 14
Initial
Bit Name Value
AL
0
DM[1:0] 00
R/W Descriptions
R/W Acknowledge Level
Specifies whether the DACK and TEND signals are
active-high or active-low.
This bit is valid only in CHCR0 and CHCR_1.
0: DACK and TEND outputs are active -low
1: DACK and TEND outputs are active -high
R/W Destination Address Mode
Specify whether the DMA destination address is
incremented, decremented, or left fixed.
00: Fixed destination address
Since the address set in DAR is not modified, the
same address is output in the second and
subsequent transfers. The address is incremented
at the first and second transfers in 16/32-byte
division transfer mode.
01: Destination address is incremented
+1 in byte units transfer
+2 in word units transfer
+4 in longword units transfer
+8 in 8-byte units transfer
+16 in 16-byte units transfer
+32 in 32-byte units transfer
10: Destination address is decremented
–1 in byte units transfer
–2 in word units transfer
–4 in longword units transfer
Setting prohibited in 8/16/32-byte units transfer
11: Fixed destination address
Set to prevent an address from being changed in the
objective modules. The address is not changed
even in 16/32-byte division transfer mode.
Example: When specifying FIFOs in the external
devices and peripheral modules.
Rev. 1.00 Sep. 19, 2007 Page 417 of 1136
REJ09B0359-0100