SH7730 Datasheet, PDF (355/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10 to 7 WR[3:0] 1010 R/W Number of Access Wait Cycles
Specify the number of wait cycles necessary for
read/write access. However, if WW[2:0] is set to a non-
zero value, the number of wait cycles for write access is
determined by the WW[2:0] setting.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
6
WM
1
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
Rev. 1.00 Sep. 19, 2007 Page 307 of 1136
REJ09B0359-0100