SH7730 Datasheet, PDF (670/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.6 Receive Control Data Register (SIRCR)
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR
can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRC0[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SIRC1[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 16 SIRC0
[15:0]
15 to 0 SIRC1
[15:0]
Initial
Value R/W
Undefined R/W
Undefined R/W
Description
Control Channel 0 Receive Data
Store data received from the SIOFRXD pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmit or receive frame is
specified by the CD0A bit in SICDAR.
• These bits are valid only when the CD0E bit in
SICDAR is set to 1.
Control Channel 1 Receive Data
Store data received from the SIOFRXD pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmit or receive frame is
specified by the CD1A bit in SICDAR.
• These bits are valid only when the CD1E bit in
SICDAR is set to 1.
Rev. 1.00 Sep. 19, 2007 Page 622 of 1136
REJ09B0359-0100