SH7730 Datasheet, PDF (850/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
(2) Data Transmission Timing
Figure 24.3 shows the data transmission timing controlled by the UART.
Basic clock for
transmission
Control register
(transmission)
During transmission of one unit of data
During transmission of
one unit of data
TXD
Transmit buffer empty
flag (status)
Transmit buffer empty
flag (interrupt)
Transmit shift buffer
empty flag (status)
Transmit shift buffer
empty flag (interrupt)
Interrupt mask
cleared
Data written to
transmit data register
Data written to
transmit data register
After the stop bit is sent at
the end of transmission,
the transmit shift buffer
empty flag (status) is set to 1.
Figure 24.3 Data Transmission Timing
Rev. 1.00 Sep. 19, 2007 Page 802 of 1136
REJ09B0359-0100