SH7730 Datasheet, PDF (220/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Data access to virtual address (VA)
VA is
in P4 area
VA is
in P2 area
VA is
in P1 area
CCR.OCE?
0
1
0
1
CCR.CB?
0
0
CCR.OCE?
1
CCR.WT?
1
Data TLB miss
exception
No
VPNs match
and V = 1
Yes
Data TLB multiple
hit exception
0 (User)
VA is in P0, U0,
or P3 area
MMUCR.AT = 1
No
Yes
No
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
Yes
No
VPNs match,
ASIDs match, and
V=1
Yes
No
Only one
entry matches
Yes
SR.MD?
1 (Privileged)
00 or
01 W
PR?
10
R/W?
R
11
R/W?
R
01 or 11
W
W _R/W?
D?
1
R
0
PR?
00 or 10
W _R/W?
R
Data TLB protection
violation exception
Initial page write
exception
Data TLB protection
violation exception
No
C = 1 and
CCR.OCE = 1
Yes
0
WT?
1
Internal resource access
Memory access
(Non-cacheable)
Cache access
in copy-back mode
Cache access
in write-through mode
Figure 7.9 Flowchart of Memory Access Using UTLB (TLB Compatible Mode)
Rev. 1.00 Sep. 19, 2007 Page 172 of 1136
REJ09B0359-0100