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| SH7730 Datasheet, PDF (1051/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series | |||
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Section 30 User Break Controller (UBC)
Hardware operations
Exception/interrupt
is generated
SPC â PC
SSR â SR
SR.BL â B'1
SR.MD â B'1
SR.RB â B'1
Exception
EXPEVT â Exception code
Exception/interrupt/trap?
Interrupt
INTEVT â Interrupt code
Trap
EXPEVT â H'160
TRA â TRAPA (imm)
SGR â R15
No
Reset exception?
Yes
(CBCR.UBDE == 1)
No
&& (user break)?
PC â DBR
PC â VBR + vector offset
Yes
PC â H'A000 0000
Debugging program
R15 â SGR
(STC instruction)
Exception handling routine
Execute RTE instruction
PC â SPC
SR â SSR
Exception operation ends
Figure 30.2 Flowchart of User Break Debugging Support Function
Rev. 1.00 Sep. 19, 2007 Page 1003 of 1136
REJ09B0359-0100
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