SH7730 Datasheet, PDF (697/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.7 Transmit and Receive Procedures
(1) Transmission in Master Mode
Figure 21.9 shows an example of settings and operation for master mode transmission.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
3
Start SIOFSCK output
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for baud rate
generator
Output serial clock
4
Set the FSE and TXE bits
in SICTR to 1
Set starting of frame synchronization
signal output and enable
transmission
Output frame synchronization
signal and issue transmit
transfer request*
5
TDREQ = 1?
No
Yes
6
Set SITDR
Set transmit data
7
Transmit SITDR from SIOFTXD
synchronously with SIOFSYNC
Transmit
Transfer
No
ended?
8
Yes
Clear the TXE bit in SICTR to 0
End
Disable transmission
End transmission
Note: * When the transmit data underflow interrupt is enabled, the TXE bit should be set to 1 after setting transmit data
at step 6.
Figure 21.9 Example of Transmit Operation in Master Mode
Rev. 1.00 Sep. 19, 2007 Page 649 of 1136
REJ09B0359-0100