SH7730 Datasheet, PDF (530/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
Figure 14.3 shows the state of output pins in software standby mode.
When the HIZCNT bit in CMNCR register of BSC is 0.
SLEEP
instruction
Oscillatoin
stop
Interrupt
request
Hi-Z
CKO
RESETOUT
STATUS0
When the HIZCNT bit in CMNCR register of BSC is 1.
SLEEP
instruction
Oscillatoin
stop
PLL oscillation
setting time*
Interrupt
request
CKO
RESETOUT
STATUS0
Note: * 300 µs is required as the PLL oscillation settling time.
PLL oscillation
setting time*
Figure 14.3 State of Output Pins on Exit from Software Standby Mode by Interrupt
Rev. 1.00 Sep. 19, 2007 Page 482 of 1136
REJ09B0359-0100