SH7730 Datasheet, PDF (273/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 8 Caches
• FLUSH transaction
When the operand cache is enabled, the FLUSH transaction checks the operand cache and if
the hit line is dirty, then the data is written back to the external memory. If the transaction is
not hit to the cache or the hit entry is not dirty, it is no-operation.
(3) Changes in Instruction Specifications Regarding Coherency Control
Of the operand cache operating instructions, the coherency control-related specifications of OCBI,
OCBP, and OCBWB have been changed from those of the SH-4A with H’20-valued VER bits in
the processor version register (PVR).
• Changes in the invalidate instruction OCBI@Rn
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H’20-valued VER bits in the processor version register (PVR). In the
SH-4A with extended functions, this instruction invalidates the operand cache line designated
by way = Rn[14:13] and entry = Rn[12:5] provided that Rn[31:24] = H’F4 (OC address array
area). In this process, writing back of the line does not take place even if the line to be
invalidated is dirty. This operation is only executable in privileged mode, and an address error
exception occurs in user mode. TLB-related exceptions do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H’F4, and their reserved areas (H’F0 to H’F3, H’F5
to H’FF).
• Changes in the purge instruction OCBP@Rn
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H’20-valued VER bits in the processor version register (PVR). In the
SH-4A with extended functions, this instruction invalidates the operand cache line designated
by way = Rn[14:13] and entry = Rn[12:5] provided that Rn[31:24] = H’F4 (OC address array
area). In this process, writing back of the line takes place when the line to be invalidated is
dirty. This operation is only executable in privileged mode, and an address error exception
occurs in user mode. TLB-related exceptions do not occur.
Do not execute this instruction to invalidate the memory-mapped array areas and control
register areas for which Rn[31:24] is not H’F4, and their reserved areas (H’F0 to H’F3, H’F5
to H’FF).
• Changes in the write-back instruction OCBWB@Rn
When Rn is designating an address in a non-cacheable area, this instruction is executed as
NOP in the SH-4A with H’20-valued VER bits in the processor version register (PVR). In the
SH-4A with extended functions, provided that Rn[31:24] = H’F4 (OC address array area), this
instruction writes back the operand cache line designated by way = Rn[14:13] and entry =
Rn[12:5] if it is dirty and clears the dirty bit to 0. This operation is only executable in
Rev. 1.00 Sep. 19, 2007 Page 225 of 1136
REJ09B0359-0100