SH7730 Datasheet, PDF (669/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.5 Transmit Control Data Register (SITCR)
SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF.
SITCR can be specified only when the FL bit in SIMDR is specified as 1xxx (x: Don't care).
SITCR is initialized by the conditions specified in table 21.3, Register State of SIOF in Each
Processing Mode, or by a transmit reset caused by the TXRST bit in SICTR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITC0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SITC1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 16 SITC0
[15:0]
Initial
Value R/W
H'0000 R/W
15 to 0 SITC1
[15:0]
H'0000 R/W
Description
Control Channel 0 Transmit Data
Specify data to be output from the SIOFTXD pin as
control channel 0 transmit data. The position of the
control channel 0 data in the transmit or receive frame
is specified by the CD0A bit in SICDAR.
• These bits are valid only when the CD0E bit in
SICDAR is set to 1.
Control Channel 1 Transmit Data
Specify data to be output from the SIOFTXD pin as
control channel 1 transmit data. The position of the
control channel 1 data in the transmit or receive frame
is specified by the CD1A bit in SICDAR.
• These bits are valid only when the CD1E bit in
SICDAR is set to 1.
Rev. 1.00 Sep. 19, 2007 Page 621 of 1136
REJ09B0359-0100