SH7730 Datasheet, PDF (779/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.8 Serial Status Register (SCASSR)
SCASSR is a 16-bit readable/writable register that indicates SCIFA states. The ORER, TSF, ER,
TDFE, BRK, RDF, or DR flag cannot be set to 1. These flags can be cleared to 0 only if they have
first been read (after being set to 1). The flags TEND, FER, and PER are read-only bits and cannot
be modified.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — ORER TSF ER TEND TDFE BRK FER PER RDF DR
Initial value: 0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
R/W: R R R R R R R/(W)*R/(W)*R/(W)* R R/(W)*R/(W)* R R R/(W)*R/(W)*
Bit
Bit Name
15 to 10 
9
ORER
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/(W)* Overrun Error Flag
Indicates that the overrun error occurred during
reception.
This bit is valid only in asynchronous mode.
0: Indicates during reception, or reception has been
completed without any error*¹
[Clearing conditions]
Power-on reset, manual reset
Writing 0 after reading ORER = 1
1: Indicates that the overrun error is generated during
reception*²
[Setting condition]
When receive FIFO is full and the next serial data
reception is completed
Notes: 1. When the RE bit in SCASCR is cleared to
0, the ORER flag is not affected and retains
its previous state.
2. SCAFRDR holds the data received before
the overrun error, and newly received data
is lost. When ORER is set to 1, subsequent
serial data reception cannot be carried out.
Rev. 1.00 Sep. 19, 2007 Page 731 of 1136
REJ09B0359-0100