SH7730 Datasheet, PDF (258/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 8 Caches
8.2 Register Descriptions
The following registers are related to cache.
Table 8.3 Register Configuration
Register Name
Abbreviation R/W P4 Address*
Area 7 Address* Size
Cache control register
CCR
R/W H'FF00 001C
H'1F00 001C
32
Queue address control register 0 QACR0
R/W H'FF00 0038
H'1F00 0038
32
Queue address control register 1 QACR1
R/W H'FF00 003C
H'1F00 003C
32
On-chip memory control register RAMCR
R/W H'FF00 0074
H'1F00 0074
32
Note: * These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 8.4 Register States in Each Processing State
Register Name
Abbreviation Power-on Reset Manual Reset
Cache control register
CCR
H'0000 0000 H'0000 0000
Queue address control register 0 QACR0
Undefined
Undefined
Queue address control register 1 QACR1
Undefined
Undefined
On-chip memory control register RAMCR
H'0000 0000 H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Rev. 1.00 Sep. 19, 2007 Page 210 of 1136
REJ09B0359-0100