SH7730 Datasheet, PDF (678/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
9
RFFULE 0
R/W Receive FIFO Full Enable
0: Disables interrupts due to receive FIFO full
1: Enables interrupts due to receive FIFO full
8
RDREQE 0
R/W Receive Data Transfer Request Enable
0: Disables interrupts due to receive data transfer
requests
1: Enables interrupts due to receive data transfer
requests
7, 6
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
SAERRE 0
R/W Slot Assign Error Enable
0: Disables interrupts due to slot assign error
1: Enables interrupts due to slot assign error
4
FSERRE 0
R/W Frame Synchronization Error Enable
0: Disables interrupts due to frame synchronization
error
1: Enables interrupts due to frame synchronization error
3
TFOVFE 0
R/W Transmit FIFO Overflow Enable
0: Disables interrupts due to transmit FIFO overflow
1: Enables interrupts due to transmit FIFO overflow
2
TFUDFE 0
R/W Transmit FIFO Underflow Enable
0: Disables interrupts due to transmit FIFO underflow
1: Enables interrupts due to transmit FIFO underflow
1
RFUDFE 0
R/W Receive FIFO Underflow Enable
0: Disables interrupts due to receive FIFO underflow
1: Enables interrupts due to receive FIFO underflow
0
RFOVFE 0
R/W Receive FIFO Overflow Enable
0: Disables interrupts due to receive FIFO overflow
1: Enables interrupts due to receive FIFO overflow
Rev. 1.00 Sep. 19, 2007 Page 630 of 1136
REJ09B0359-0100