SH7730 Datasheet, PDF (561/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
16.5.3 Buffer Operation
TPUn_TGRC and TPUn_TGRD can be used as buffer registers.
Table 16.9 shows the register combinations used in buffer operation.
Table 16.9 Register Combinations in Buffer Operation
Timer General Register
TPUn_TGRA
TPUn_TGRB
Buffer Register
TPUn_TGRC
TPUn_TGRD
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. Updating timing to rewrite from buffer registers can be
selected either when compare match occurs or when the counter is cleared.
This operation is illustrated in figure 16.8.
Counter clear signal
BFWT bit
Buffer register
Compare match signal
Timer general
register
Comparator
TPU0_TCNT
Figure 16.8 Compare Match Buffer Operation
Rev. 1.00 Sep. 19, 2007 Page 513 of 1136
REJ09B0359-0100