SH7730 Datasheet, PDF (155/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 5 Exception Handling
(4) Instruction TLB Multiple Hit Exception
• Source: Multiple ITLB address matches
• Transition address: H'A0000000
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections.
(5) Data TLB Multiple-Hit Exception
• Source: Multiple UTLB address matches
• Transition address: H'A0000000
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections.
Rev. 1.00 Sep. 19, 2007 Page 107 of 1136
REJ09B0359-0100