SH7730 Datasheet, PDF (104/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
3.3 Instruction Set
Table 3.3 shows the notation used in the SH instruction lists shown in tables 3.4 to 3.13.
Table 3.3 Notation Used in Instruction List
Item
Instruction
mnemonic
Format
OP.Sz SRC, DEST
Operation
notation
Instruction code MSB ↔ LSB
Description
OP:
Sz:
SRC:
DEST:
Rm:
Rn:
imm:
disp:
Operation code
Size
Source operand
Source and/or destination operand
Source register
Destination register
Immediate data
Displacement
→, ← Transfer direction
(xx)
Memory operand
M/Q/T SR flag bits
&
Logical AND of individual bits
|
Logical OR of individual bits
∧
Logical exclusive-OR of individual bits
~
Logical NOT of individual bits
<<n, >>n n-bit shift
mmmm: Register number (Rm, FRm)
nnnn: Register number (Rn, FRn)
0000: R0, FR0
0001: R1, FR1
:
1111: R15, FR15
mmm: Register number (DRm, XDm, Rm_BANK)
nnn: Register number (DRn, XDn, Rn_BANK)
000: DR0, XD0, R0_BANK
001: DR2, XD2, R1_BANK
:
111: DR14, XD14, R7_BANK
mm: Register number (FVm)
nn:
Register number (FVn)
00:
FV0
01:
FV4
10:
FV8
11:
FV12
iiii:
Immediate data
dddd: Displacement
Rev. 1.00 Sep. 19, 2007 Page 56 of 1136
REJ09B0359-0100