SH7730 Datasheet, PDF (828/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 24 IrDA Interface (IrDA)
24.3.1 IrDA Test Register (IRIF_INT2)
IRIF_INT2 is a test register and must not be modified.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IRDA
TH
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
15 to 1
Bit Name
—
0
IRDATH
Initial
Value
All 0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W This bit is used for IrDA test purposes only and must
not be modified.
24.3.2 DMA Receive Interrupt Source Clear Register (IRIF_RINTCLR)
IRIF_RINTCLR is a register that clears a request for DMA transfer of received data.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDMAC[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: W W W W W W W W W W W W W W W W
Bit
15 to 0
Bit Name
RDMAC
[15:0]
Initial
Value
H'0000
R/W Description
W Clear of DMA Transfer Request for Received Data
To clear a request, write any word data to this register.
Rev. 1.00 Sep. 19, 2007 Page 780 of 1136
REJ09B0359-0100