SH7730 Datasheet, PDF (88/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 2 Programming Model
(4) Floating-Point Status/Control Register (FPSCR)
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FR SZ PR DN
Cause
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
15
0
R/W
14 13
Cause
00
R/W R/W
12
0
R/W
11
0
R/W
10 9 8
Enable (EN)
000
R/W R/W R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
Flag
0
R/W
3
0
R/W
2
0
R/W
10
RM
01
R/W R/W
Bit
Bit Name
31 to 22 —
21
FR
20
SZ
19
PR
18
DN
Initial
Value
All 0
0
0
0
1
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1
are assigned to XF0 to XF15
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1
are assigned to FR0 to FR15
Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
pair (64 bits)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5.
Precision Mode
0: Floating-point instructions are executed as
single-precision operations
1: Floating-point instructions are executed as
double-precision operations (graphics support
instructions are undefined)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5
Denormalization Mode
0: Denormalized number is treated as such
1: Denormalized number is treated as zero
Rev. 1.00 Sep. 19, 2007 Page 40 of 1136
REJ09B0359-0100