SH7730 Datasheet, PDF (909/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 26 A/D Converter
26.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte (bits 15 to 6) of the A/D data register. Bits 5 to 0 of an A/D data register are always read as 0.
Table 26.4 indicates the pairings of analog input channels and A/D data registers.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
AD[9:0]
——————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value R/W Description
15 to 6 AD[9:0] All 0 R
Bit data (10 bits)
5 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 26.4 Analog Input Channels and A/D Data Registers
Analog Input Channel
AN0
AN1
AN2
AN3
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
Rev. 1.00 Sep. 19, 2007 Page 861 of 1136
REJ09B0359-0100