SH7730 Datasheet, PDF (132/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 4 Pipelining
Table 4.4 Issue Rates and Execution Cycles
Functional
Category No. Instruction
Data transfer 1
instructions
2
EXTS.B
EXTS.W
Rm,Rn
Rm,Rn
3 EXTU.B
Rm,Rn
4 EXTU.W Rm,Rn
5 MOV
Rm,Rn
6 MOV
#imm,Rn
7 MOVA
@(disp,PC),R0
8 MOV.W
@(disp,PC),Rn
9 MOV.L
@(disp,PC),Rn
10 MOV.B
@Rm,Rn
11 MOV.W
@Rm,Rn
12 MOV.L
@Rm,Rn
13 MOV.B
@Rm+,Rn
14 MOV.W
@Rm+,Rn
15 MOV.L
@Rm+,Rn
16 MOV.B
@(disp,Rm),R0
17 MOV.W
@(disp,Rm),R0
18 MOV.L
@(disp,Rm),Rn
19 MOV.B
@(R0,Rm),Rn
20 MOV.W
@(R0,Rm),Rn
21 MOV.L
@(R0,Rm),Rn
22 MOV.B
@(disp,GBR),R0
23 MOV.W
@(disp, GBR),R0
24 MOV.L
@(disp, GBR),R0
25 MOV.B
Rm,@Rn
26 MOV.W
Rm,@Rn
27 MOV.L
Rm,@Rn
28 MOV.B
Rm,@-Rn
29 MOV.W
Rm,@-Rn
Instruction
Execution Execution
Group
Issue Rate Cycles Pattern
EX
1
1
2-1
EX
1
1
2-1
EX
1
1
2-1
EX
1
1
2-1
MT
1
1
2-4
MT
1
1
2-3
LS
1
1
2-2
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
LS
1
1
3-1
Rev. 1.00 Sep. 19, 2007 Page 84 of 1136
REJ09B0359-0100