SH7730 Datasheet, PDF (558/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
(b) Free-running count operation and periodic count operation
Immediately after a reset, the TPUn_TCNT counters are all designated as free-running counters.
When the relevant bit in TPUn_TSTR is set to 1, the corresponding TPUn_TCNT counter starts
up-count operation as a free-running counter. When TPUn_TCNT has overflowed (changes from
H'FFFF to H'0000), the TCFV bit in TPUn_TSR is set to 1. TPUn_TCNT starts counting up again
from H'0000 after an overflow.
Figure 16.3 illustrates free-running counter operation.
TPUn_TCNT value
H'FFFF
H'0000
CST bit
Time
TCFV
Figure 16.3 Free-Running Counter Operation
When a compare match is selected as the TPUn_TCNT clearing source, the TPUn_TCNT counter
for the relevant channel performs periodic count operation. The TPUn_TGR register for setting
the period is designated as an output compare register, and counter clearing by compare match is
selected by means of bits CCLR[2:0] in TPUn_TCR. After the settings have been made,
TPUn_TCNT starts count-up operation as a periodic counter when the corresponding bit in
TPUn_TSTR is set to 1. When the count value matches the value in TPUn_TGR, the TGF bit in
TPUn_TSR is set to 1 and TPUn_TCNT is cleared to H'0000.
After a compare match, TPUn_TCNT starts counting up again from H'0000.
Rev. 1.00 Sep. 19, 2007 Page 510 of 1136
REJ09B0359-0100