SH7730 Datasheet, PDF (886/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
When no parity error occurs
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitter output
When a parity error occurs in T=0 mode
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Transmitter output
When a parity error occurs in T=1 mode
Receiver output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitter output
Ds: Start bit, D0 to D7: Data bit, Dp: Parity bit, DE: Error signal
Figure 25.2 Data Format Used by Smart Card Interface
The operation sequence is as follows.
1. When not in use, the data line is in a high-impedance state and fixed at high level by a pull-up
resistance.
2. The transmit side initiates transmission of one frame of data. The data frame begins with the
start bit (Ds: low level). This is followed by eight data bits (D0 to D7) and the parity bit (Dp).
3. The smart card interface then returns the data line to high impedance. The data line is held at
high level by the pull-up resistance.
4. The receive side performs a parity check.
If there is no parity error and reception is normal, reception of the next frame is awaited,
without further action.
On the other hand, when a parity error has occurred in T = 0 mode, an error signal (DE: low
level) is output, requesting data retransmission. After output of an error signal with the
specified duration, the receive side again sets the signal line to the high-impedance state. The
signal line returns to high level by means of the pull-up resistance. If in T = 1 mode, however,
no error signal is output even if a parity error occurs.
5. If the transmit side does not receive an error signal, the next frame is transmitted.
On the other hand, if in T = 0 mode and an error signal is received, the data for which the error
occurred is retransmitted as in step 2 above. In T = 1 mode, however, error signals are not
received and retransmission is not performed.
Rev. 1.00 Sep. 19, 2007 Page 838 of 1136
REJ09B0359-0100