SH7730 Datasheet, PDF (100/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Addressing Instruction
Mode
Format
Effective Address Calculation Method
Calculation
Formula
Register
indirect
with pre-
decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
Rn – 1/2/4 _–
Rn – 1/2/4/8
Quadword:
Rn – 8 → Rn
1/2/4
Rn → EA
(Instruction
executed
with Rn after
calculation)
Register
@(disp:4, Rn) Effective address is register Rn contents with
indirect with
4-bit displacement disp added. After disp is
displacement
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the operand
size.
Rn
disp
(zero-extended)
+
Rn + disp × 1/2/4
Byte: Rn + disp
→ EA
Word: Rn + disp
× 2 → EA
Longword:
Rn + disp × 4 →
EA
×
Indexed
register
indirect
@(R0, Rn)
1/2/4
Effective address is sum of register Rn and R0
contents.
Rn
+
Rn + R0
Rn + R0 → EA
R0
Rev. 1.00 Sep. 19, 2007 Page 52 of 1136
REJ09B0359-0100