SH7730 Datasheet, PDF (679/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.9 FIFO Control Register (SIFCTR)
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TFWM[2:0]
TFUA[4:0]
RFWM[2:0]
RFUA[4:0]
Initial value: 0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R R R R R R/W R/W R/W R R R R R
Initial
Bit
Bit Name Value
15 to 13 TFWM[2:0] 000
12 to 8 TFUA[4:0] 10000
R/W
R/W0
R
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
transmit FIFO are empty.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages
of the transmit FIFO are empty.
101: Issue a transfer request when 8 or more stages of
the transmit FIFO are empty.
110: Issue a transfer request when 4 or more stages of
the transmit FIFO are empty.
111: Issue a transfer request when 1 or more stages of
transmit FIFO are empty.
• A transfer request to the transmit FIFO is issued by
the TDREQE bit in SISTR.
• The transmit FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
Transmit FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (full) to B'10000 (empty).
Rev. 1.00 Sep. 19, 2007 Page 631 of 1136
REJ09B0359-0100