SH7730 Datasheet, PDF (737/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
0
LOOP
0
R/W Loop-Back Test
Internally connects the transmit output pin (TXD) and
receive input pin (RXD) and internally connects the RTS
pin and CTS pin and enables loop-back testing.
0: Loop back test disabled
1: Loop back test enabled
22.3.10 FIFO Data Count Set Register (SCFDR)
SCFDR is a 16-bit register that indicates the quantity of data stored in SCFTDR and SCFRDR.
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of
receive data in SCFRDR with the lower 8 bits. SCFDR can always be read by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
———
TFDC[4:0]
———
RFDC[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Bit Name
15 to 13 —
Initial
Value
All 0
12 to 8 TFDC[4:0] 00000
7 to 5 —
All 0
4 to 0 RFDC[4:0] 00000
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Number of Data Bytes in Transmit FIFO
Indicate the quantity of non-transmitted data stored in
SCFTDR. H'00 means no transmit data, and H'10
means that SCFTDR is full of transmit data (16 bytes).
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Number of Data Bytes in Receive FIFO
Indicate the quantity of receive data stored in SCFRDR.
H'00 means no receive data, and H'10 means that
SCFRDR full of receive data (16 bytes).
Rev. 1.00 Sep. 19, 2007 Page 689 of 1136
REJ09B0359-0100