SH7730 Datasheet, PDF (454/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
12.3 Register Descriptions
Table 12.2 shows the configuration of registers of the DMAC. Table 12.3 shows the state of
registers in each processing mode. The SAR for channel 0 is expressed such as SAR_0.
Table 12.2 Register Configuration of DMAC
Channel Name
0
DMA source address register_0
DMA destination address register_0
DMA transfer count register_0
DMA channel control register_0
1
DMA source address register_1
DMA destination address register_1
DMA transfer count register_1
DMA channel control register_1
2
DMA source address register_2
DMA destination address register_2
DMA transfer count register_2
DMA channel control register_2
3
DMA source address register_3
DMA destination address register_3
DMA transfer count register_3
DMA channel control register_3
Common DMA operation register
4
DMA source address register_4
DMA destination address register_4
DMA transfer count register_4
DMA channel control register_4
5
DMA source address register_5
DMA destination address register_5
DMA transfer count register_5
DMA channel control register_5
Abbreviation R/W
SAR_0
R/W
DAR_0
R/W
TCR_0
R/W
CHCR_0
R/W
SAR_1
R/W
DAR_1
R/W
TCR_1
R/W
CHCR_1
R/W
SAR_2
R/W
DAR_2
R/W
TCR_2
R/W
CHCR_2
R/W
SAR_3
R/W
DAR_3
R/W
TCR_3
R/W
CHCR_3
R/W
DMAOR
R/W
SAR_4
R/W
DAR_4
R/W
TCR_4
R/W
CHCR_4
R/W
SAR_5
R/W
DAR_5
R/W
TCR_5
R/W
CHCR_5
R/W
Address
Access
Size
H'FE008020 32
H'FE008024 32
H'FE008028 32
H'FE00802C 32
H'FE008030 32
H'FE008034 32
H'FE008038 32
H'FE00803C 32
H'FE008040 32
H'FE008044 32
H'FE008048 32
H'FE00804C 32
H'FE008050 32
H'FE008054 32
H'FE008058 32
H'FE00805C 32
H'FE008060 16
H'FE008070 32
H'FE008074 32
H'FE008078 32
H'FE00807C 32
H'FE008080 32
H'FE008084 32
H'FE008088 32
H'FE00808C 32
Rev. 1.00 Sep. 19, 2007 Page 406 of 1136
REJ09B0359-0100