SH7730 Datasheet, PDF (1033/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
3. The OCBI instruction is handled as longword write access without the data value, and
the PREF, OCBP, and OCBWB instructions are handled as longword read access
without the data value. Therefore, do not include the data value in the match conditions
for these instructions.
30.2.2 Match Operation Setting Registers 0 and 1 (CRR0 and CRR1)
CRR0 and CRR1 are readable/writable 32-bit registers which specify the operation to be executed
when channels 0 and 1 satisfy the match condition, respectively. The following operations can be
set in the CRR0 and CRR1 registers: (1) breaking at a desired timing for the instruction fetch cycle
and (2) requesting a break.
• CRR0
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCB BIE
Initial value : 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R/W R/W
Bit
Bit Name
31 to 14 —
13
—
12 to 2 —
Initial
Value
All 0
1
All 0
R/W Description
R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
R Reserved
This bit is always read as 1. The write value should
always be 1.
R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
Rev. 1.00 Sep. 19, 2007 Page 985 of 1136
REJ09B0359-0100