SH7730 Datasheet, PDF (111/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 3 Instruction Set
Table 3.8 Branch Instructions
Instruction
Operation
Instruction Code
BF
label When T = 0, disp × 2 + PC +
4 → PC
When T = 1, nop
10001011dddddddd
BF/S
label
Delayed branch; when T = 0, disp × 2 +
PC + 4 → PC
When T = 1, nop
10001111dddddddd
BT
label When T = 1, disp × 2 + PC +
4 → PC
When T = 0, nop
10001001dddddddd
BT/S
label
Delayed branch; when T = 1, disp × 2 +
PC + 4 → PC
When T = 0, nop
10001101dddddddd
BRA
label Delayed branch, disp × 2 +
PC + 4 → PC
1010dddddddddddd
BRAF
Rn Delayed branch, Rn + PC + 4 → PC
0000nnnn00100011
BSR
label Delayed branch, PC + 4 → PR,
disp × 2 + PC + 4 → PC
1011dddddddddddd
BSRF
Rn Delayed branch, PC + 4 → PR, Rn + PC 0000nnnn00000011
+ 4 → PC
JMP
@Rn Delayed branch, Rn → PC
0100nnnn00101011
JSR
@Rn Delayed branch, PC + 4 → PR, Rn → PC 0100nnnn00001011
RTS
Delayed branch, PR → PC
0000000000001011
Privileged T Bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 3.9 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
ICBI
@Rn
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC
Rm,SGR
LDC
Rm,SSR
LDC
Rm,SPC
Operation
0 → MACH, MACL
0→S
0→T
Invalidates instruction cache block
Rm → SR
Rm → GBR
Rm → VBR
Rm → SGR
Rm → SSR
Rm → SPC
Instruction Code
0000000000101000
0000000001001000
0000000000001000
0000nnnn11100011
0100mmmm00001110
0100mmmm00011110
0100mmmm00101110
0100mmmm00111010
0100mmmm00111110
0100mmmm01001110
Privileged T Bit
—
—
—
—
—
0


Privileged LSB
—
—
Privileged —
Privileged —
Privileged —
Privileged —
Rev. 1.00 Sep. 19, 2007 Page 63 of 1136
REJ09B0359-0100