SH7730 Datasheet, PDF (736/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5, 4
TTRG[1:0] 00
R/W Transmit FIFO Data Trigger
Set the quantity of remaining transmit data at which the
transmit FIFO data register empty (TDFE) flag in
SCFSR is set. The TDFE flag is set to 1 when the
quantity of transmit data in SCFTDR has become equal
to or less than the set trigger number shown below as
the transmission proceeds.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of
empty bytes in SCFTDR when the TDFE
flag is set to 1.
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
In clock synchronous mode, MCE bit should always be
0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the
input value, and RTS is also fixed at 0.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Invalidates the transmit data in SCFTDR to reset
SCFTDR in an empty state.
0: Resetting disabled*
1: Resetting enabled
Note: * Resetting is performed by a power-on reset
or manual reset, or when a standby state is
entered.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Invalidates the receive data in SCFRDR to reset
SCFRDR in an empty state.
0: Resetting disabled*
1: Resetting enabled
Note: * Resetting is performed by a power-on reset
or manual reset, or when a standby state is
entered.
Rev. 1.00 Sep. 19, 2007 Page 688 of 1136
REJ09B0359-0100