SH7730 Datasheet, PDF (352/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Bit
12, 11
10 to 7
Initial
Bit Name Value R/W
SW[1:0] 00
R/W
WR[3:0] 1010 R/W
Description
Number of Delay Cycles from Address/CSn Assertion to
RD/WEn Assertion
Specify the number of delay cycles from address and
CSn assertion to RD or WEn assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Number of Access Wait Cycles
Specify the number of wait cycles necessary for
read/write access. However, if WW[2:0] is set to a non-
zero value, the number of wait cycles for write access is
determined by the WW[2:0] setting.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Rev. 1.00 Sep. 19, 2007 Page 304 of 1136
REJ09B0359-0100