SH7730 Datasheet, PDF (663/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
4
SYNCDL 0
R/W Data Pin Bit Delay for SIOFSYNC Pin
Valid when the SIOFSYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode.
0: No bit delay
1: 1-bit delay
3 to 0 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 21.4 shows the operation in each transfer mode.
Table 21.4 Operation in Each Transfer Mode
Transfer Mode Master/Slave SIOFSYNC
Bit Delay
Control Data Method*
Slave mode 1
Slave
Synchronous
pulse
SYNCDL bit
Slot position
Slave mode 2
Slave
Synchronous
pulse
Secondary FS
Master mode 1 Master
Synchronous
pulse
Slot position
Master mode 2 Master
L/R
No
Not supported
Note: * The control data method is valid only when the FL bit is specified as 1xxx (x: Don't
care).
Rev. 1.00 Sep. 19, 2007 Page 615 of 1136
REJ09B0359-0100