SH7730 Datasheet, PDF (733/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
22.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that is used to set the bit rate of serial transmission/reception in relation
to the operating clock of the baud rate generator selected by the CKS1[1:] bits in SCSMR.
The CPU can always read and write to SCBRR.
Bit: 7
6
5
4
3
2
1
0
SCBRD[7:0]
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
7 to 0
Bit Name
Initial
Value
SCBRD[7:0] H'FF
R/W Description
R/W Bit rate setting
The SCBRR setting is calculated as follows:
• Asynchronous mode:
N = {Pφ / (64 × 2^2n-1 × B)} × 10⁶ – 1
• Clock synchronous mode:
N = {Pφ / (8 × 2^2n-1 × B)} × 10⁶ – 1
B:
Bit rate (bits/s)
N:
SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n:
Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 22.4.)
Rev. 1.00 Sep. 19, 2007 Page 685 of 1136
REJ09B0359-0100