SH7730 Datasheet, PDF (497/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
Section 13 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates the CPU clock (Iφ), SH clock (Sφ), bus
clock (Bφ), and peripheral clock (Pφ). The CPG consists of an oscillator, a PLL circuit, and a
divider.
13.1 Features
• Four clocks generated for LSI internal operation
The CPU clock (Iφ) used by the CPU, FPU, cache, and TLB, SH clock (Sφ) used by the
SuperHyway bus, bus clock (Bφ) used by the external bus interface, and peripheral clock (Pφ)
used by the peripheral modules can be generated independently.
• Clock modes
The combination of the division ratios for the CPU clock, SH clock, bus clock, and peripheral
clock after a power-on reset can be selected from three clock modes.
• Frequency change function
The frequency of the CPU clock, SH clock, bus clock, SDRAM clock, and peripheral clock
can be changed independently using the PLL circuit and dividers within the CPG. Frequencies
are changed by software using the frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped in sleep mode and software standby mode, and specific modules can
be stopped using the module standby function. See section 14, Reset and Power-Down Modes,
for details.
Rev. 1.00 Sep. 19, 2007 Page 449 of 1136
REJ09B0359-0100