SH7730 Datasheet, PDF (935/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 28 I/O Port
28.2 Port A
Port A is an input/output port with the pin configuration shown in figure 28.1. Each pin has an
input pull-up MOS, which is controlled by the port A control register (PACR) in the PFC.
Port A
PTA7 (input/outout)/D23 (input/output)
PTA6 (input/output)/D22 (input/output)
PTA5 (input/output)/D21 (input/output)
PTA4 (input/output)/D20 (input/output)
PTA3 (input/output)/D19 (input/output)
PTA2 (input/output)/D18 (input/output)
PTA1 (input/output)/D17 (input/output)
PTA0 (input/output)/D16 (input/output)
Figure 28.1 Port A
28.2.1 Port A Data Register (PADR)
PADR is a register that stores data for pins PTA7 to PTA0. Bits PA7DT to PA0DT correspond to
pins PTA7 to PTA0. For pins that function as general-purpose output pins, a read operation
directly reads out the corresponding value from this register. For pins that function as general-
purpose input pins, a read operation reads out the level on the corresponding pin.
Bit: 7
6
5
4
3
2
1
0
PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
PA7DT
0
R/W Table 28.3 shows the function of PADR.
6
PA6DT
0
R/W
5
PA5DT
0
R/W
4
PA4DT
0
R/W
3
PA3DT
0
R/W
2
PA2DT
0
R/W
1
PA1DT
0
R/W
0
PA0DT
0
R/W
Rev. 1.00 Sep. 19, 2007 Page 887 of 1136
REJ09B0359-0100