SH7730 Datasheet, PDF (301/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.3.4 Interrupt Priority Registers A to K (IPRA to IPRK)
IPRA to IPRK are 16-bit registers that specify priority levels from 15 to 0 for on-chip peripheral
module interrupts.
On-chip peripheral module interrupts are assigned to four 4-bit groups in each register. These 4-bit
groups are set with values from H'F (1111) to H'0 (0000) to specify the interrupt priority level for
the corresponding interrupt. Setting H'F means priority level 15 (the highest level); H'0 means
priority level 0 (interrupt request is masked).
Bit: _{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
IPR0n
IPR1n
IPR2n
IPR3n
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 12 IPR0n
H'0
11 to 8 IPR1n
H'0
R/W These bits set the priority level for each interrupt source
R/W ^{in 4-bit units. For details, see table 10.4.}
7 to 4 IPR2n
H'0
R/W
3 to 0 IPR3n
H'0
R/W
Table 10.4 Interrupt Sources and IPRA to IPRK
Register IPR0n
IPR1n
IPR2n
IPR3n
IPRA
TMU0
TMU1
TMU2
RTC
IPRB


SIM
—
IPRC
—
—
—
—
IPRD
PINTA0 to PINTA7 PINTB0 to PINTB3 IrDA0
IrDA1
IPRE
DMAC (1)
DMAC (2)

ADC
IPRF



CMT
IPRG
SCIF0
SCIF1
SCIF2
SCIF3
IPRH
SCIF4
SCIF5

IIC0
IPRI
SIOF
—

IIC1
IPRJ

—

—
IPRK
TPU0
TPU1
—

Note: —: Reserved. An undefined value will be read. The write value should always be 0.
Rev. 1.00 Sep. 19, 2007 Page 253 of 1136
REJ09B0359-0100