SH7730 Datasheet, PDF (335/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.3.4 Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select word (16 bits) or longword (32 bits) on power-on reset. The memory bus width of the other
area is set by the register. The correspondence between the memory type, external pins (MD3),
and bus width is listed in the table below.
Table 11.5 Correspondence between External Pins (MD3), Memory Type of CS0, and
Memory Bus Width
MD3
0
1
Memory Type
Normal memory
Bus Width
16 bits
32 bits
11.3.5 Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at power-on reset as shown in table 11.6.
Table 11.6 Correspondence between External Pin (MD5) and Data Alignment
MD5
0
1
Data Alignment
Big endian
Little endian
Rev. 1.00 Sep. 19, 2007 Page 287 of 1136
REJ09B0359-0100