SH7730 Datasheet, PDF (448/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
The bus sequence is as follows. The address bus and data bus are placed in a high-impedance
state synchronized with the rising edge of CKO. The bus mastership enable signal is asserted 0.5
cycles after the above timing, synchronized with the falling edge of CKO. The bus control signals
(BS, CSn, RAS, CAS, DQMxx, WEn, RD, and RDWR) are placed in the high-impedance state at
subsequent rising edges of CKO. Bus request signals are sampled at the falling edge of CKO.
The sequence for reclaiming the bus mastership from a slave is described below. 1.5 cycles after
the negation of BREQ is detected at the falling edge of CKO, the bus control signals are driven
high. The BACK is negated at the next falling edge of the clock. The fastest timing at which
actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKO
where address and data signals are driven. Figure 11.44 shows the bus arbitration timing.
In an original slave device designed by the user, multiple bus accesses are generated continuously
to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh
correctly, the slave device must be designed to release the bus mastership within the refresh
interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership
while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus
mastership is received. If the slave releases the bus, the LSI acquires the bus mastership to
execute the SDRAM refresh.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
CKO
BREQ
BACK
A25 to A0
D31 to D0
CSn
Other bus
control signals
Figure 11.44 Bus Arbitration Timing
Rev. 1.00 Sep. 19, 2007 Page 400 of 1136
REJ09B0359-0100