SH7730 Datasheet, PDF (782/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Initial
Bit
Bit Name
Value R/W Description
4
BRK
0
R/(W)* Break Detection
Indicates that a break signal is detected in received
data in asynchronous mode.
0: No break signal is being received
[Clearing conditions]
• Power-on reset, manual reset
• BRK is read as 1, then written to with 0
1: A break signal is received *
[Setting conditions]
Data including a framing error is received
• A framing error with space 0 occurs in the
subsequent received data
Note: * When a break is detected, transfer of the
received data (H'00) to SCAFRDR stops
after detection. When the break ends and
the receive signal becomes mark 1, the
transfer of the received data resumes.
3
FER
0
R
Framing Error
Indicates a framing error in the data read from
SCAFRDR in asynchronous mode.
0: No framing error occurred in the data read from
SCAFRDR
[Clearing conditions]
• Power-on reset, manual reset
• No framing error is present in the data read from
SCAFRDR
1: A framing error occurred in the data read from
SCAFRDR
[Setting condition]
• A framing error is present in the data read from
SCAFRDR
Rev. 1.00 Sep. 19, 2007 Page 734 of 1136
REJ09B0359-0100