SH7730 Datasheet, PDF (919/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 26 A/D Converter
26.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 26.5 shows the A/D
conversion timing. Table 26.5 indicates the A/D conversion time.
As indicated in figure 26.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 26.5.
In multi mode and scan mode, the values given in table 26.5 apply to the first conversion. In the
second and subsequent conversions the conversion the conversion time is fixed at 512 states
(fixed) when CKS[1:0] = 10, 256 states (fixed) when CKS[1:0] = 01, and 128 states (fixed) when
CKS[1:0] = 00.
*¹
Pφ
Address
*²
Write
signal
Input sampling
timing
ADF
t_D
t_SPL
t_CONV
t_D
t_SPL
t_CONV
Notes:
A/D conversion start delay
Input sampling time
A/D conversion time
1. ADCSR write cycle
2. ADCSR address
Figure 26.5 A/D Conversion Timing
Rev. 1.00 Sep. 19, 2007 Page 871 of 1136
REJ09B0359-0100