SH7730 Datasheet, PDF (587/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 17 Realtime Clock (RTC)
Initial
Bit
Bit Name Value
R/W Description
2, 1
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
AF
0
R/W Alarm Flag
The AF flag is set when the alarm time, which is set by
an alarm register (ENB bit in RSECAR, RMINAR,
RHRAR, RWKAR, RDAYAR, RMONAR, or RYRAR is
set to 1), and counter match.
0: Alarm register and counter not match
[Clearing condition]
When 0 is written to AF.
1: Alarm register and counter match*
[Setting condition]
When alarm register (only a register with ENB bit set to
1) and counter match
Note: * Writing 1 holds previous value.
17.3.17 RTC Control Register 2 (RCR2)
RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit
RESET, and RTC count control.
RCR2 is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by
a manual reset. It is not initialized in standby mode, and retains its contents.
Bit: 7
6
5
4
3
2
1
0
PEF
PES[2:0]
RTCEN ADJ RESET START
Initial value: 0
0
0
0
1
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 539 of 1136
REJ09B0359-0100