SH7730 Datasheet, PDF (1155/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
SCIF_SCK
t_SCKW
t_SCKR
t_Scyc
t_SCKF
Figure 33.52 SCK Input Clock Timing
SCIFn_SCK
SCIFn_TxD
(data transmission)
SCIFn_RxD
(data reception)
SCIFn_RTS
SCIFn_CTS
t_Scyc
t_TXD
t_RTSD
t_RXS t_RXH
t_CTSS t_CTSH
Figure 33.53 SCI Input/Output Timing in Synchronous Mode
33.4.14 SIM Module Signal Timing
Table 33.16 SIM Module Signal Timing
Conditions: V_CCQ = 3.0 to 3.6 V, V_CC = 1.1 to 1.3 V, AV_CC = 3.0 to 3.6 V, Ta = -20 to 75°C
Item
Symbol Min.
SIM_CLK clock cycle
t_SMCYC
2/t_Pcyc
SIM_CLK clock high level width
t_SMCWH
0.4 × t_SMCYC
SIM_CLK clock low level width
t_SMCWL
0.4 × t_SMCYC
SIM_RST reset output delay
t
0
SMRD
Note: t_Pcyc is the cycle time of the peripheral clock (Pφ).
Max.
16/t_Pcyc


20
Unit Figure
ns 33.54
ns
ns
ns
Rev. 1.00 Sep. 19, 2007 Page 1107 of 1136
REJ09B0359-0100