SH7730 Datasheet, PDF (519/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
20

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
19
MSTP019 0
R/W Module Stop Bit 019
Setting this bit to 1 halts supply of the clock signal to
the H-UDI.
0: H-UDI operates
1: Clock supply to H-UDI halted
18
MSTP018 0
R/W Module Stop Bit 018
Setting this bit to 1 halts supply of the clock signal to
the debugging module (DBG) of the LSI. Clear this bit
to 0 when using the H-UDI, UBC, or AUD.
0: DBG operates
1: Clock supply to DBG halted
17
MSTP017 0
R/W Module Stop Bit 017
Setting this bit to 1 halts supply of the clock signal to
the UBC. Clear this bit to 0 when using the H-UDI or
AUD.
0: UBC operates
1: Clock supply to UBC halted
16
MSTP016 0
R/W Module Stop Bit 016
Setting this bit to 1 halts supply of the clock signal to
the debugging module (SUBC).
0: SUBC operates
1: Clock supply to SUBC halted
15
MSTP015 0
R/W Module Stop Bit 015
Setting this bit to 1 halts supply of the clock signal to
the TMU.
0: TMU operates
1: Clock supply to TMU halted
Rev. 1.00 Sep. 19, 2007 Page 471 of 1136
REJ09B0359-0100