SH7730 Datasheet, PDF (30/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
Figure 7.1 Role of MMU............................................................................................................ 149
Figure 7.2 Virtual Address Space (AT in MMUCR= 0) ............................................................ 150
Figure 7.3 Virtual Address Space (AT in MMUCR= 1) ............................................................ 151
Figure 7.4 P4 Area...................................................................................................................... 152
Figure 7.5 Physical Address Space............................................................................................. 154
Figure 7.6 UTLB Configuration (TLB Compatible Mode) ........................................................ 168
Figure 7.7 Relationship between Page Size and Address Format (TLB Compatible Mode)...... 170
Figure 7.8 ITLB Configuration (TLB Compatible Mode).......................................................... 171
Figure 7.9 Flowchart of Memory Access Using UTLB (TLB Compatible Mode)..................... 172
Figure 7.10 Flowchart of Memory Access Using ITLB (TLB Compatible Mode) .................... 173
Figure 7.11 UTLB Configuration (TLB Extended Mode).......................................................... 174
Figure 7.12 Relationship between Page Size and Address Format (TLB Extended Mode) ....... 177
Figure 7.13 ITLB Configuration (TLB Extended Mode) ........................................................... 177
Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode) ...................... 179
Figure 7.15 Flowchart of Memory Access Using ITLB (TLB Extended Mode)........................ 180
Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode).................................... 183
Figure 7.17 Operation of LDTLB Instruction (TLB Extended Mode) ....................................... 184
Figure 7.18 Memory-Mapped ITLB Address Array................................................................... 196
Figure 7.19 Memory-Mapped ITLB Data Array (TLB Compatible Mode) ............................... 197
Figure 7.20 Memory-Mapped ITLB Data Array 1 (TLB Extended Mode)................................ 198
Figure 7.21 Memory-Mapped ITLB Data Array 2 (TLB Extended Mode)................................ 199
Figure 7.22 Memory-Mapped UTLB Address Array ................................................................. 201
Figure 7.23 Memory-Mapped UTLB Data Array (TLB Compatible Mode).............................. 202
Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode) .............................. 202
Figure 7.25 Memory-Mapped UTLB Data Array 2 (TLB Extended Mode) .............................. 203
Section 8 Caches
Figure 8.1 Configuration of Operand Cache (Cache size = 32 Kbytes) ..................................... 207
Figure 8.2 Configuration of Instruction Cache (Cache size = 32 Kbytes).................................. 208
Figure 8.3 Configuration of Write-Back Buffer ......................................................................... 220
Figure 8.4 Configuration of Write-Through Buffer.................................................................... 220
Figure 8.5 Memory-Mapped IC Address Array (Cache size = 32 Kbytes) ................................ 228
Figure 8.6 Memory-Mapped IC Data Array (Cache size = 32 Kbytes)...................................... 229
Figure 8.7 Memory-Mapped OC Address Array (Cache size = 32 Kbytes)............................... 231
Figure 8.8 Memory-Mapped OC Data Array (Cache size = 32 Kbytes) .................................... 232
Figure 8.9 Store Queue Configuration........................................................................................ 233
Section 10 Interrupt Controller (INTC)
Figure 10.1 Block Diagram of INTC.......................................................................................... 244
Figure 10.2 Example of IRL Interrupt Connection..................................................................... 263
Rev. 1.00 Sep. 19, 2007 Page xxx of xlviii