SH7730 Datasheet, PDF (545/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
16.4.1 Timer Control Register (TPUn_TCR)
TPUn_TCR controls the TPUn_TCNT for each channel. The TPU has one TPUn_TCR register
for each channel. TPUn_TCR is initialized to H'0000 at a reset.
TPUn_TCR register settings should be made only while TPUn_TCNT operation is stopped.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
CCLR[2:0]
CKEG[1:0]
TPSC[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 8 —
All 0 R
Reserved
These bits are always read as 0 and cannot be
modified.
7 to 5 CCLR[2:0] 000
R/W Counter Clear
Select the TPUn_TCNT clearing source.
000: TPUn_TCNT clearing disabled
001: TPUn_TCNT cleared by TPUn_TGRA compare
match
010: TPUn_TCNT cleared by TPUn_TGRB compare
match
011: Setting prohibited
100: TPUn_TCNT clearing disabled
101: TPUn_TCNT cleared by TPUn_TGRC compare
match
110: TPUn_TCNT cleared by TPUn_TGRD compare
match
111: Setting prohibited
Rev. 1.00 Sep. 19, 2007 Page 497 of 1136
REJ09B0359-0100