SH7730 Datasheet, PDF (1035/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
1
PCB
0
R/W PC Break Select
Specifies either before or after instruction execution as
the break timing for the instruction fetch cycle. This bit
is invalid for breaks other than ones for the instruction
fetch cycle.
0: Sets the PC break before instruction execution.
1: Sets the PC break after instruction execution.
0
BIE
0
R/W Break Enable
Specifies whether or not to request a break when the
match condition is satisfied for the channel.
0: Does not request a break.
1: Requests a break.
30.2.3 Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be
included in the break conditions for channels 0 and 1, respectively.
• CAR0
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CA
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CA
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
CA
Initial
Value
Undefined
R/W
R/W
Description
Compare Address
Specifies the address to be included in the break
conditions.
When the operand bus has been specified using the
CBR0 register, specify the SAB address in CA[31:0].
Rev. 1.00 Sep. 19, 2007 Page 987 of 1136
REJ09B0359-0100