SH7730 Datasheet, PDF (313/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
If a flag is updated while the BL bit is 0, execution may branch to the interrupt handling routine
with INTEVT = 0; interrupt handling may start depending on the timing relationship between flag
updating and interrupt request detection in the LSI. In this case, operation can be continued
without causing any problems by executing the RTE instruction.
10.4.6 Interrupt Exception Handling and Priority
Tables 10.6 and 10.7 show the interrupt sources, the codes for the interrupt event register
(INTEVT), and the interrupt priority.
Each interrupt source is assigned to a unique INTEVT code. The start address of the exception
handling routine is common for all interrupt sources. This is why, for instance, the value of
INTEVT is used as an offset at the start of the exception handling routine to branch execution in
order to identify the interrupt source.
On-chip peripheral module interrupt priorities can be set freely between 15 and 0 for each module
by using IPRA to IPRK. A reset assigns priority level 0 to the on-chip peripheral module
interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority is determined according to the default priority
indicated at the right in tables 10.6 and 10.7.
Interrupt priority registers and interrupt mask registers must be updated only while the BL bit in
SR is set to 1. To prevent accepting unintentional interrupts, read any interrupt priority register
and then clear the BL bit to 0, which ensures the necessary interval for internal processing.
Rev. 1.00 Sep. 19, 2007 Page 265 of 1136
REJ09B0359-0100