SH7730 Datasheet, PDF (767/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3 Register Descriptions
The register configuration of the SCIFA is shown in table 23.2, and the register states in each
processing mode are shown in table 23.3.
Table 23.2 Register Configuration
Register Name
Abbreviation R/W
Address
Serial mode register A4
SCASMR4
R/W
H'FFE4 0000
Bit rate register A4
SCABRR4
R/W
H'FFE4 0004
Serial control register A4
SCASCR4
R/W
H'FFE4 0008
Transmit data stop register A4
SCATDSR4
R/W
H'FFE4 000C
FIFO error count register A4
SCAFER4
R
H'FFE4 0010
Serial status register A4
SCASSR4
R/W* H'FFE4 0014
FIFO control register A4
SCAFCR4
R/W
H'FFE4 0018
FIFO data count register A4
SCAFDR4
R
H'FFE4 001C
Transmit FIFO data register A4
SCAFTDR4
W
H'FFE4 0020
Receive FIFO data register A4
SCAFRDR4
R
H'FFE4 0024
Serial mode register A5
SCASMR5
R/W
H'FFE5 0000
Bit rate register A5
SCABRR5
R/W
H'FFE5 0004
Serial control register A5
SCASCR5
R/W
H'FFE5 0008
Transmit data stop register A5
SCATDSR5
R/W
H'FFE5 000C
FIFO error count register A5
SCAFER5
R
H'FFE5 0010
Serial status register A5
SCASSR5
R/W* H'FFE5 0014
FIFO control register A5
SCAFCR5
R/W
H'FFE5 0018
FIFO data count register A5
SCAFDR5
R
H'FFE5 001C
Transmit FIFO data register A5
SCAFTDR5
W
H'FFE5 0020
Receive FIFO data register A5
SCAFRDR5
R
H'FFE5 0024
Note: * To bits 9 to 7, 5, 4, 1, and 0, only 0 can be written to clear the flag.
Access Size
16
8
16
8
16
16
16
16
8
8
16
8
16
8
16
16
16
16
8
8
Rev. 1.00 Sep. 19, 2007 Page 719 of 1136
REJ09B0359-0100