SH7730 Datasheet, PDF (342/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.4.2 CSn Space Bus Control Register (CSnBCR)
This register specifies the type of memory connected to each space, data-bus width of each space,
and the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the CSnBCR initialization is completed.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
Bit: 31 30
——
Initial value: 0
0
R/W: R R
Bit: 15 14
ADR
SFIX
—
Initial value: 0
0
R/W: R/W R
29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — BAS —
WW[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R R R R R R R/W R R/W R/W R/W
13 12 11 10 9
8
7
6
5
4
3
2
1
0
— SW[1:0]
WR[3:0]
WM — — — — HW[1:0]
0
0
0
1
0
1
0
1
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30 to 28 IWW[2:0] 011
R/W Idle Cycles between Write-Read Cycles and Write-Write
Cycles
These bits specify the number of idle cycles to be
inserted after the access to a memory that is connected
to the space. The target access cycles are the write-
read cycle and write-write cycle.
000: Reserved
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Rev. 1.00 Sep. 19, 2007 Page 294 of 1136
REJ09B0359-0100