SH7730 Datasheet, PDF (875/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
Initial
Bit
Bit Name Value R/W Description
5
ORER
0
R/(W*) Overrun Error
Indicates that an overrun error occurred during
reception, resulting in abnormal termination.
0: Indicates that reception is in progress, or that
reception was completed normally*¹
[Clearing conditions]
• On reset
• When 0 is written to the ORER bit
1: Indicates that an overrun error occurred during
reception*²
[Setting condition]
• When the RDRF bit is set to 1 and the next serial
reception is completed.
Notes: 1. When the RE bit in SCSCR is cleared to 0,
the ORER flag is unaffected and the
previous state is retained.
2. In SCRDR, the received data before the
overrun error occurred is lost, and the data
that had been received at the time when the
overrun error occurred is retained. Further,
with the ORER bit set to 1, subsequent
serial reception cannot be continued.
4
ERS
0
R/(W*) Error Signal Status
Indicates the status of error signals returned from the
receive side during transmission. In T = 1 mode, this
flag is not set.
0: Indicates that an error signal indicating detection of a
parity error was not sent from the receive side
[Clearing conditions]
• On reset
• When 0 is written to the ERS bit
1: Indicates that an error signal indicating detection of a
parity error was sent from the receive side
[Setting condition]
• When an error signal is sampled.
Note: Even if the TE bit in SCSCR is cleared to 0, the
ERS flag is unaffected, and the previous state is
retained.
Rev. 1.00 Sep. 19, 2007 Page 827 of 1136
REJ09B0359-0100