SH7730 Datasheet, PDF (562/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 16 16-Bit Timer Pulse Unit (TPU)
(1) Example of Buffer Operation Setting Procedure
Figure 16.9 shows an example of the buffer operation setting procedure.
Buffer operation
Set buffer operation
[1] [1] Designate TPUn_TGR for buffer operation
with bits BFA and BFB in TPUn_TMDR.
Set rewrite timing
[2]
[2] Set the rewrite timing with the BFWT bit
in TPUn_TMDR.
Set external pin function _[3]
[3] Set external pin function by pin function
controller (PFC).
Start count
[4] Set the CST bit in TPUn_TSTR to 1 to
[4]
start the count operation.
<Buffer operation>
Figure 16.9 Example of Buffer Operation Setting Procedure
(2) Examples of buffer operation
Figure 16.10 shows an operation example in which PWM mode has been designated for channel 0,
and buffer operation has been designated for TPUn_TGRA and TPUn_TGRC. The settings used
in this example are TPUn_TCNT clearing by compare match B, 1-output (TPUn_TO0 to
TPUn_TO3 pins) at compare match A, initial value 0 output by counter clearing, and the rewrite
timing from buffer register at counter clearing.
When compare match A occurs, the output changes. When a counter clear is generated by
TPUn_TGRB, the output changes and the value in buffer register TPUn_TGRC is simultaneously
transferred to the timer general register TPUn_TGRA. This operation is repeated every time
compare match A occurs.
For details on PWM modes, see section 16.5.4, PWM Modes.
Rev. 1.00 Sep. 19, 2007 Page 514 of 1136
REJ09B0359-0100